1. Field of the Invention
The present invention relates to digital phase-locked loops (PLLs), and in particular, to phase-frequency detectors (PFDs) used in such digital PLLs.
2. Description of the Related Art
Referring to FIG. 1, a conventional PFD that has been used in many digital PLL designs includes two D-type flip-flops 12u, 12d and a logic AND gate 14. The flip-flops 12u, 12d are separately clocked by the reference signal REF and feedback signal FB. With each rising edge of these input signals REF, FB, a logic one (VDD applied at the D-input) is clocked through to the output Q of each flip-flop 12u, 12d. The data output signals Q of the flip-flops 12u, 12d form the xe2x80x9cpump upxe2x80x9d. UP and xe2x80x9cpump downxe2x80x9d DN signals used for controlling a charge pump circuit 20. Whenever the reference signal REF leads the feedback signal FB in phase, the pump up signal UP is asserted. Conversely, when the feedback signal FB leads the reference signal REF in phase, the pump down signal DN is asserted. When the pump up signal UP is asserted (and inverted by the inverter 18 within the charge pump 20), the output pull-up transistor P1 is turned on, thereby causing electrical charge to be pumped to the output terminal 21. Conversely, when the pump down signal DN is asserted, the output pull-down transistor N1 is turned on, thereby causing electrical charge to be sunk from the output terminal 21.
The logic AND gate 14 ensures that the data output signals Q of the flip-flops 12u, 12d are cleared in the event that both the pump up signal UP and pump down signal DN become asserted simultaneously.
A logic OR gate 16 can be included, as shown, so as to enable the user to place the PFD 10 in a high impedance state. By asserting the control signal HiZ, the output 17 of the logic OR gate 16 is also asserted, thereby clearing both output signals Q of the flip-flops 12u, 12d. With both of these signals UP, DN in their cleared, or unasserted, states, both output transistors P1, N1 of the charge pump are turned off, thereby leaving the output terminal 21 of the charge pump 20 in a high impedance state.
This type of PFD 10 is widely used due to the advantages afforded by its transfer function. As is well known, this type of PFD 10 has a transfer function such that the output signal 23 of the charge pump 20, due to the control signals UP, DN provided by the PFD 10, depends upon the phase difference between the two input signals REF, FB when the host PLL is in its phase-locked state, and depends upon the frequency difference between the input signals REF, FB when the host PLL is in its unlocked state. Accordingly, a digital PLL in which this PFD 10 is used will lock under any condition, in terms of the input signals REF, FB, regardless of the type of loop filter in use.
Referring to FIG. 2, by way of example, the timing diagrams are shown for the input REF, FB and output UP, DN signals when the host PLL (not shown) is not phase-locked, in this case with the feedback signal FB being slightly lower in frequency than the reference signal REF. Since the feedback signal FB lags the reference signal REF, the net output of the PFD 10 is xe2x80x9cup,xe2x80x9d i.e., the pump up signal UP is asserted, thereby seeking to increase the output frequency of the host PLL and, therefore, increase the frequency of the feedback signal FB. Accordingly, the duty cycle of this PFD output UP gradually increases until the point in time when the feedback signal FB lags the reference signal REF by approximately 360xc2x0, or 2xcfx80 radians, in phase (at approximately the 300 nanosecond point in time for this example). At this point in time, the duty cycle of the PFD output UP changes from being nearly 100% to 0%.
Referring to FIG. 3, most loop filters 22 have low pass frequency characteristics and typically consist of a serially-connected resistor R and capacitor C1 connected in shunt with another capacitor C2, as shown. When the duty cycle of the PFD output signal UP is high, and particularly as it is increasing, the voltage 23 across the loop filter 22 rises. Hence, this loop filter voltage 23 is higher at the end of each successive charge pump update. However, when the duty cycle is low, and particularly as it is decreasing, this loop filter voltage 23 decreases even though the net charge being delivered to the loop filter 22 by the positive pulses of the PFD signal UP continues to be positive. This is due to the fact that most loop filters 22 use second order loop filters, such as that shown here, where the series capacitors C1 has a larger capacitance value than the shunt capacitor C2. As a result, before the loop filter 22 achieves its final state of equilibrium, the voltage on the smaller capacitor C2 is higher than the voltage across the larger capacitor C1. Hence, if the duty cycle of the PFD output signal UP (or DN) is not high enough, the net change of the loop filter output voltage 23 can be negative.
A phase-frequency detector (PFD) in accordance with the presently claimed invention has increased phase error gain during acquisition of phase lock when used in a phase-locked loop (PLL). The reference and feedback signals are time-multiplexed into N pairs of input signals. Each pair of input signals is detected by one of N phase-frequency detectors, which produce N pairs of detection signals indicative of phase differences between the reference and feedback signals. These N pairs of detection signals are combined to produce frequency increase and decrease control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. These control signals have respective substantially nonzero signal values that vary in respective relations to the difference between the reference and feedback signal phases when such phase difference is less than 2xcfx80 radians, and repeat with patterns having phase difference intervals of 2Nxcfx80 radians when such phase difference is greater than 2xcfx80 radians.
In accordance with one embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes routing circuitry, phase-frequency detection circuitry and combining circuitry. The routing circuitry receives and selectively routes reference and feedback signals having respective signal frequencies and phases to provide respective pluralities of reference and feedback signals. The phase-frequency detection circuitry, coupled to the routing circuitry, receives and detects the pluralities of reference and feedback signals to provide a plurality of detection signals having respective substantially nonzero signal values that vary in respective relations to: a difference between the reference and feedback signal phases when the signal phase difference is less than 2xcfx80 radians; and a difference between the reference and feedback signal frequencies when the signal phase difference is greater than 2xcfx80 radians. The combining circuitry, coupled to the phase-frequency detection circuitry, combines the plurality of detection signals to provide: a frequency increase control signal indicative of when the feedback signal frequency is lower than the reference signal frequency; and a frequency decrease control signal indicative of when the feedback signal frequency is higher than the reference signal frequency.
In accordance with another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes input circuitry, output circuitry and a plurality N of phase-frequency detection circuits. The input circuitry receives reference and feedback signals having respective signal frequencies and phases and in response thereto provides a plurality of input signals. The output circuitry receives a plurality of output signals and in response thereto provides first and second control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. The plurality N of phase-frequency detection circuits, coupled between the input and output circuitry, processes the plurality of input signals to provide the plurality of output signals. The first and second control signals have respective substantially nonzero signal values that: vary in respective relations to a difference between the reference and feedback signal phases when the signal phase difference is less than 2xcfx80 radians; and repeat with patterns having phase difference intervals of 2Nxcfx80 radians when the signal phase difference is greater than 2xcfx80 radians.
In accordance with still another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes router means, phase-frequency detector means and combiner means. The router means is for receiving and selectively routing reference and feedback signals having respective signal frequencies and phases and providing respective pluralities of reference and feedback signals. The phase-frequency detector means is for receiving and detecting the pluralities of reference and feedback signals and providing a plurality of detection signals having respective substantially nonzero signal values that vary in respective relations to: a difference between the reference and feedback signal phases when the signal phase difference is less than 2xcfx80 radians; and a difference between the reference and feedback signal frequencies when the signal phase difference is greater than 2xcfx80 radians. The combiner means is for combining the plurality of detection signals and providing: a frequency increase control signal indicative of when the feedback signal frequency is lower than the reference signal frequency; and a frequency decrease control signal indicative of when the feedback signal frequency is higher than the reference signal frequency.
In accordance with yet another embodiment of the presently claimed invention, a PFD having increased phase error gain during acquisition of phase lock when used in a PLL includes input means, output means and phase-frequency detector means. The input means is for receiving reference and feedback signals having respective signal frequencies and phases and in response thereto providing a plurality 2N of input signals. The output means is for receiving a plurality 2N of output signals and in response thereto providing first and second control signals indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. The phase-frequency detector means is for processing the plurality 2N of input signals and providing the plurality 2N of output signals. The first and second control signals have respective substantially nonzero signal values that: vary in respective relations to a difference between the reference and feedback signal phases when the signal phase difference is less than 2xcfx80 radians; and repeat with patterns having phase difference intervals of 2Nxcfx80 radians when the signal phase difference is greater than 2xcfx80 radians.